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FEATURES 2 Matched ADCs on Single Chip 50 MSPS Conversion Speed On-Board Voltage Reference Low Power (<1 W) Low Input Capacitance (10 pF) 65 V Power Supplies Flexible Input Range APPLICATIONS Quadrature Demodulation for Communications Digital Oscilloscopes Electronic Warfare Radar
ENCODE
Dual 8-Bit 50 MSPS A/D Converter AD9058
FUNCTIONAL BLOCK DIAGRAM
AD9058
+VREF 8-BIT ANALOGTO-DIGITAL CONVERTER
8 A
AIN
-VREF
2VREF
+VREF ENCODE 8-BIT ANALOGTO-DIGITAL CONVERTER 8 B
GENERAL DESCRIPTION
The AD9058 combines two independent, high performance, 8-bit analog-to-digital converters (ADCs) on a single monolithic IC. Combined with an optional on-board voltage reference, the AD9058 provides a cost-effective alternative for systems requiring two or more ADCs. Dynamic performance (SNR, ENOB) is optimized to provide up to 50 MSPS conversion rates. The unique architecture results in low input capacitance while maintaining high performance and low power (<0.5 W/channel). Digital inputs and outputs are TTL compatible. Performance has been optimized for an analog input of 2 V p-p ( 1 V; 0 V to 2 V). Using the on-board 2 V voltage reference, the AD9058 can be set up for unipolar positive operation (0 V to 2 V). This internal voltage reference can drive both ADCs. Commercial (0C to 70C) and military (-55C to +125C) temperature range parts are available. Parts are supplied in hermetic 48-lead DIP and 44-lead "J" lead packages.
RF
AIN
-VREF
QUADRATURE RECEIVER
G
8
Q
90
AD9058
8 G I
LO
REV. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD9058-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes ANALOG INPUT Input Bias Current Input Resistance Input Capacitance Analog Bandwidth REFERENCE INPUT Reference Ladder Resistance Ladder Tempco Reference Ladder Offset (Top) Reference Ladder Offset (Bottom) Offset Drift Coefficient INTERNAL VOLTAGE REFERENCE Reference Voltage Temperature Coefficient Power Supply Rejection Ratio (PSRR) SWITCHING PERFORMANCE Maximum Conversion Rate2 Aperture Delay (tA) Aperture Delay Matching Aperture Uncertainty (Jitter) Output Delay (Valid) (tV)2 Output Delay (tV) Tempco Propagation Delay (tPD)2 Propagation Delay (tPD) Tempco Output Time Skew ENCODE INPUT Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance Pulsewidth (High) Pulsewidth (Low) 25C Full 25C Full Full 25C Full 25C 25C 25C 25C Full Full 25C Full 25C Full Full 25C Full Full 25C 25C 25C 25C 25C 25C Full 25C Full 25C Full Full Full Full 25C 25C 25C I VI I VI VI I VI I IV V I VI V I VI I VI V I VI V I I IV IV V I V I V V VI VI VI VI V I I
[ VS = 5 V; VREF = 2 V (internal); ENCODE = 40 MSPS; AIN = 0 V to 2 V; -VREF = GROUND, unless otherwise noted.]1 All specifications apply to either of the two ADCs.
Test Level AD9058AJD/AJJ Min Typ Max 8 0.25 0.5 Guaranteed 75 12 28 10 175 170 0.45 8 8 50 1.95 1.90 2.0 150 10 50 0.8 0.2 10 8 16 12 -16 1 25 50 0.1 2.20 2.25 1.95 1.90 170 340 12 15 0.65 0.8 1.3 1.4 AD9058AKD/AKJ Min Typ Max 8 0.25 0.5 Guaranteed 75 28 10 175 170 0.45 8 8 50 2.0 150 10 60 0.8 0.2 10 8 16 12 -16 1 25 2.20 2.25 170 340 15 A A k pF MHz /C mV mV mV mV V/C V V V/C mV/V MSPS ns ns ps, rms ns ps/C ns ps/C ns V V A A pF ns ns 0.5 0.7 1.0 1.25 Unit Bits LSB LSB LSB LSB
Temp
120 80
220 270 16 24 23 33
120 80
220 270 16 24 23 33
0.1
1.5 05
1.5 0.5
5
19
2 0.8 600 1000 5 8 8
2 0.8 600 1000 5 8 8
-2-
REV. D
AD9058
Parameter DYNAMIC PERFORMANCE Transient Response Overvoltage Recovery Time Effective Number of Bits (ENOB)3 Analog Input @ 2.3 MHz @ 10.3 MHz Signal-to-Noise Ratio3 Analog Input @ 2.3 MHz @ 10.3 MHz Signal-to-Noise Ratio3 (Without Harmonics) Analog Input @ 2.3 MHz @ 10.3 MHz Second Harmonic Distortion Analog Input @ 2.3 MHz @ 10.3 MHz Third Harmonic Distortion Analog Input @ 2.3 MHz @ 10.3 MHz Crosstalk Rejection4 DIGITAL OUTPUTS Logic "1" Voltage (IOH = 2 mA) Logic "0" Voltage (IOL = 2 mA) POWER SUPPLY5 +VS Supply Current -VS Supply Current Power Dissipation Temp 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C Full Full Full Full Full Test Level V V I I I I I I I I I I IV VI VI VI VI VI 2.4 0.4 127 27 770 154 38 960 127 27 770 AD9058AJD/AJJ Min Typ Max 2 2 7.7 7.4 48 46 48 47 58 58 58 58 60 7.2 7.1 45 44 46 45 48 48 50 50 48 2.4 0.4 154 38 960 AD9058AKD/AKJ Min Typ Max 2 2 7.7 7.4 48 46 48 47 58 58 58 58 60 Unit ns ns Bits Bits dB dB dB dB dBc dBc dBc dBc dBc V V mA mA mW
NOTES 1 For applications in which +V S may be applied before -V S, or +V S current is not limited to 500 mA, a reverse-biased clamping diode should be inserted between ground and -VS to prevent destructive latch up. See section entitled "Using the AD9058." 2 To achieve guaranteed conversion rate, connect each data output to ground through a 2 k pull-down resistor. 3 SNR performance limits for the 48-lead DIP "D" package are 1 dB less than shown. ENOB limits are degraded by 0.3 dB. SNR and ENOB measured with analog input signal 1 dB below full scale at specified frequency. 4 Crosstalk rejection measured with full-scale signals of different frequencies (2.3 MHz and 3.5 MHz) applied to each channel. With both signals synchronously encoded at 40 MSPS, isolation of the undesired frequency is measured with an FFT. 5 Applies to both A/Ss and includes internal ladder dissipation. Specifications subject to change without notice.
REV. D
-3-
AD9058
ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE Model
AD9058AJJ
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . -1.5 V to +2.5 V +VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V -VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.8 V to -6 V2 Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +VS Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Voltage Reference Current . . . . . . . . . . . . . . . . . . . . . . 53 mA +VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 V -VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5 V Operating Temperature Range AD9058AJD/AJJ/AKD/AKJ . . . . . . . . . . . . . . . 0C to 70C Maximum Junction Temperature3 AD9058AJD/AJJ/AKD/AKJ . . . . . . . . . . . . . . . . . . . 150C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300C
NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 For applications in which +V S may be applied before -V S, or +V S current is not limited to 500 mA, a reverse-biased clamping diode should be inserted between ground and -VS to prevent destructive latch up. See section entitled "Using the AD9058." 3 Typical thermal impedances: 44-lead hermetic J-leaded ceramic package: JA = 86.4C/W; JC = 24.9C/W; 48-lead hermetic: DIP JA = 40C/W; JC = 12C/W.
Temperature Range
0C to 70C
Description
Package Option1
J-44 J-44 J-44 J-44 D-48 D-48 D-48
44-Lead J-Leaded Ceramic2 AD9058AJJ-REEL 0C to 70C 44-Lead J-Leaded Ceramic2 AD9058AKJ 0C to 70C 44-Lead J-Leaded Ceramic, AC Tested AD9058ATJ/8833 -55C to +125C 44-Lead J-Leaded Ceramic, AC Tested AD9058AJD 0C to 70C 48-Lead Ceramic DIP AD9058AKD 0C to 70C 48-Lead Ceramic DIP, AC Tested AD9058ATD/8833 -55C to +125C 48-Lead Ceramic DIP, AC Tested
NOTES 1 D = Hermetic ceramic DIP package; J = leaded ceramic package. 2 Hermetically sealed ceramic package; footprint equivalent to PLCC. 3 For specifications, refer to Analog Devices Military Products Databook.
EXPLANATION OF TEST LEVELS
Test Level I. 100% production tested. II. 100% production tested at 25C, and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. All devices are 100% production tested at 25C. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/industrial devices.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9058 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
+VS 5V
WARNING!
ESD SENSITIVE DEVICE
+VS
13k
D0-D7* +VINT +VREF COMP
-VREF AIN** ENCODE** +VS +5V -5.2V
DIGITAL BITS
ENCODE
0.1 F
AD9058
GROUND
-VS
* INDICATES EACH PIN IS CONNECTED THROUGH 2k ** INDICATES EACH PIN IS CONNECTED THROUGH 100
Equivalent Digital Outputs
Equivalent Encode Circuit
Burn-In Connections
-4-
REV. D
AD9058
PIN CONFIGURATIONS
GROUND ENCODE
GROUND GROUND
1 2 3 4 5 6 7 8 9 48 47 46 45 44 43 42 41 40 39 38
D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) GROUND -VS GROUND
+VS GROUND
+VS AIN
COMP
+VREF
+VINT
+VS
AIN
+VREF
NC
-VREF
40 39 -VS -VREF +VS ENCODE
6 7 -VS -VREF +VS ENCODE D7 (MSB) D6 D5 D4 D3 D2 D1 17
-VS NC AIN +VS
GROUND 10 +VREF 11 COMP 12 +VINT 13
AD9058
TOP VIEW (Not to Scale)
D7 (MSB) D6 D5 D4 D3 D2 GROUND D1 29
+VS TOP VIEW 36 +V S (Not to Scale) 35 GROUND +VREF 14
37 34 33 32 31 30 29 28 27 26 25
AD9058
GROUND 15 +VS 16 AIN 17 NC 18 -VS
19
-VS GROUND D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB)
-VREF 20 GROUND 21 +VS 22 ENCODE 23 GROUND 24
+VS
GROUND
D0 (LSB)
GROUND
GROUND
NC = NO CONNECT
GROUND
D0 (LSB)
-VS
+VS
-VS
NC
18
28
NC = NO CONNECT
AD9058AJJ/AKJ Pinouts
PIN FUNCTION DESCRIPTIONS
AD9058AJD/AKD Pinouts
J-Lead Pin Number ADC-A ADC-B 3 43 4 42 5 41 6 40 7 39 8 38 9 37 10 36 11 35 12-17 34-29 18 28 19 27 20 26 21 25 22 24 COMMON PINS 1 2
Mnemonic +VREF GROUND +VS AIN -VS -VREF +VS ENCODE D7 (MSB) D6-D1 D0 (LSB) GROUND -VS GROUND +VS COMP +VINT
Function Top of Internal Voltage Reference Ladder Analog Ground Return Positive 5 V Analog Supply Voltage Analog Input Voltage Negative 5 V Supply Voltage Bottom of Internal Voltage Reference Ladder Positive 5 V Digital Supply Voltage TTL Compatible Convert Command Most Significant Bit of TTL Digital Output TTL Compatible Digital Output Bits Least Significant Bit of TTL Digital Output Digital Ground Return Negative 5 V Supply Voltage Analog Ground Return Positive 5 V Analog Supply Voltage Connection for External (0.1 F) Compensation Capacitor Internal 2 V Reference; Can Drive +VREF for Both ADCs
Ceramic DIP Pin Number ADC-A ADC-B 14 11 15 10 16 9 17 8 19 6 20 5 22 3 23 2 25 48 26-31 47-42 32 41 21, 24, 33 1, 4, 40 34 39 35 38 36 37 COMMON PINS 12 13
REV. D
-5-
AD9058
THEORY OF OPERATION
ANALOG IN +VREF 128
INTERPOLATING LATCHES
DECODE LOGIC
The AD9058 contains two separate 8-bit analog-to-digital converters (ADCs) on a single silicon die. The two devices can be operated independently with separate analog inputs, voltage references, and clocks. In a traditional flash converter, 256 input comparators are required to make the parallel conversion for 8-bit resolution. This is in marked contrast to the scheme used in the AD9058, as shown in Figure 1. Unlike traditional "flash," or parallel, converters, each of the two ADCs in the AD9058 utilizes a patented interpolating architecture to reduce circuit complexity, die size, and input capacitance. These advantages accrue because, compared to a conventional flash design, only half the normal number of input comparator cells is required to accomplish the conversion. In this unit, each of the two independent ADCs uses only 128 (27) comparators to make the conversion. The conversion for the seven most significant bits (MSBs) is performed by the 128 comparators. The value of the least significant bit (LSB) is determined by interpolation between adjacent comparators in the decoding register. A proprietary decoding scheme processes the comparator outputs and provides an 8-bit code to the output register of each ADC; the scheme also minimizes error codes.
127
256
LATCHES
8 CLOCK 8 CLOCK
8
8
2
-VREF
1
Figure 1. Comparator Block Diagram
Analog input range is established by the voltages applied at the voltage reference inputs (+VREF and -VREF). The AD9058 can operate from 0 V to 2 V using the internal voltage reference, or anywhere between -1 V and +2 V using external references. Input range is limited to 2 V p-p when using external references. The internal resistor ladder divides the applied voltage reference into 128 steps, with each step representing two 8-bit quantization levels.
1k ENCODE 50 74HCT04 10pF
10 ENCODE A
36 ENCODE B 5, 9, 22, 24, 37, 41
8 400 200 5 AD9617 800 2 -2V 0.1 F 20k AD707 20k 0.1 F 43 800 400 200 ANALOG IN B 0.5V AD9617 5 0.1 F 40 1 +2V 3 6 38
-VREF A -VREF B
+VS
+5V
D0A(LSB) AIN A
+VINT D7A(MSB) +VREF A D0B(LSB)
+VREF B
COMP
AIN B
D7B(MSB)
28 29 30 31 32 33 34 35 7, 20, 26, 39
AD9058
(J-LEAD)
-VS 0.1 F
-5V (SEE TEXT) 1N4001
4, 19, 21, 25, 27, 42
Figure 2. AD9058 Using Internal 2 V Voltage Reference
-6-
74HCT 273
74HCT 273
ANALOG IN A 0.5V
18 17 16 15 14 13 12 11
REV. D
AD9058
1k +5V 1 AD580 2 10k 10k +5V 1/2 AD708 0.1 F 20k 400 ANALOG IN A 0.125V 50 AD9618 5 1V 6 AIN A 0.1 F 150 2N3904 10 3 43 3 10 ENCODE A 36 ENCODE B +VS +VREF A +VREF B D0A(LSB) 18 17 16 15 14 13 12 11 5, 9, 22, 24, 37, 41 0.1 F RZ1 +5V ENCODE 50k 74ACT04 10pF
74ACT 273
8
20k 10k 1/2 AD708 150 2N3906 -5V 400 ANALOG IN B 0.125V 50 5k AD9618 1V 40 1 AIN B COMP 0.1 F 38 -1V -VREF B 8
D7A(MSB) -VREF A D0B(LSB)
CLOCK 28 29 30 31 32 33 34 35 7, 20, 26, 39 -VS 0.1 F RZ2
74ACT 273
8
D7B(MSB)
0.1 F
CLOCK -5V (SEE TEXT) 1N4001
AD9058
(J-LEAD)
4, 19, 21, 25, 27, 42
Figure 3. AD9058 Using External Voltage References
The on-board voltage reference, +VINT, is a band gap reference that has sufficient drive capability for both reference ladders. It provides a 2 V reference that can drive both ADCs in the AD9058 for unipolar positive operation (0 V to 2 V). USING THE AD9058 Refer to Figure 2. Using the internal voltage reference connected to both ADCs as shown reduces the number of external components required to create a complete data acquisition system. The input ranges of the ADCs are positive unipolar in this configuration, ranging from 0 V to 2 V. Bipolar input signals are buffered, amplified, and offset into the proper input range of the ADC using a good low distortion amplifier such as the AD9617 or AD9618. The AD9058 offers considerable flexibility in selecting the analog input ranges of the ADCs; the two independent ADCs can even have different input ranges if required. In Figure 3, the AD9058 is shown configured for 1 V operation. The "Reference Ladder Offset" shown in the specifications table refers to the error between the voltage applied to the +VREF (top) or -VREF (bottom) of the reference ladder and the voltage required at the analog input to achieve a 1111 1111 or 0000 0000 transition. This indicates the amount of adjustment range that must be designed into the reference circuit for the AD9058. The diode shown between ground and -VS is normally reversebiased and is used to prevent latch-up. Its use is recommended for applications in which power supply sequencing might allow +VS to be applied before -VS; or the +VS supply is not current REV. D
limited. If the negative supply is allowed to float (the +5 V supply is powered up before the -5 V supply), substantial +5 V supply current will attempt to flow through the substrate (VS supply contact) to ground. If this current is not limited to <500 mA, the part may be destroyed. The diode prevents this potentially destructive condition from occurring. Timing Refer to the AD9058 Timing Diagram, Figure 4. The AD9058 provides latched data outputs with no pipeline delay. To conserve power, the data outputs have relatively slow rise and fall times. When designing system timing, it is important to observe (1) setup and hold times; and (2) the intervals when data is changing. Figure 3 shows 2 k pull-down resistors on each of the D0-D7 output data bits. When operating at conversion rates higher than 40 MSPS, these resistors help equalize rise and fall times and ease latching the output data into external latches. The 74ACT logic family devices have short setup and hold times and are the recommended choices for speeds of 40 MSPS or more. Layout To ensure optimum performance, a single low impedance ground plane is recommended. Analog and digital grounds should be connected together and to the ground plane at the AD9058 device. Analog and digital power supplies should be bypassed to ground through 0.1 F ceramic capacitors as close to the unit as possible. For prototyping or evaluation, surface-mount sockets are available from Methode Electronics, Inc. (Part No. 213-0320602) for evaluating AD9058 surface-mount packages. To evaluate the -7-
AD9058
AD9058 in through-hole PCB designs, use the AD9058AJD/AKD with individual pin sockets (AMP Part No. 6-330808-0). Alternatively, surface-mount AD9058 units can be mounted in a through-hole socket (Circuit Assembly Corporation, Irvine, California Part No. CA-44SPC-T). AD9058 APPLICATIONS Combining two ADCs in a single package is an attractive alternative in a variety of systems when cost, reliability, and space are important considerations. Different systems emphasize particular specifications, depending on how the part is used. In high density digital radio communications, a pair of high speed ADCs are used to digitize the in-phase (I) and quadrature (Q) components of a modulated signal. The signal presented to each ADC in this type of system consists of message-dependent amplitudes varying at the symbol rate, which is equal to the sample rates of the converters.
N ANALOG INPUT
the time required for the AD9058 to achieve full accuracy when a step function input is applied. Overvoltage recovery time is the interval required for the AD9058 to recover to full accuracy after an overdriven analog input signal is reduced to its input range. Time domain performance of the ADC is also extremely important in digital oscilloscopes. When a track-/sample-and-hold is used ahead of the ADC, its operation becomes similar to that described above for receivers. The dynamic response to high frequency inputs can be described by the effective number of bits (ENOB). The effective number of bits is calculated with a sine wave curve fit and is expressed as:
ENOB = N - LOG2 Error (measured ) Error (ideal )
[
]
where N is the resolution (number of bits) and measured error is actual rms error calculated from the converter's outputs with a pure sine wave applied as the input. Maximum conversion rate is defined as the encode (sample) rate at which SNR of the lowest frequency analog test signal drops no more than 3 dB below the guaranteed limit.
60
tA
N+1 N+2
ENCODE HARMONIC DISTORTION - dB
+125 C
tV
D0-D7 VALID DATA FOR N-1 VALID DATA FOR N VALID DATA FOR N+1 DATA CHANGING
55
+25 C -55 C
50
tPD
45
tA = APERTURE TIME tV = DATA DELAY OF PRECEDING ENCODE tPD = OUTPUT PROPAGATION DELAY
40
Figure 4. Timing Diagram
35
Figure 5 shows what the analog input to the AD9058 would look like when observed relative to the sample clock. Signal-tonoise ratio (SNR), transient response, and sample rate are all critical specifications in digitizing this "eye pattern."
ANALOG INPUT
55
30 0.1
1 10 INPUT FREQUENCY - MHz
100
Figure 6. Harmonic Distortion vs. Analog Input Frequency
50 +25 C AND +125 C
8.0
SAMPLE CLOCK
Figure 5. I and Q Input Signals
45
7.2
Receiver sensitivity is limited by the SNR of the system. For the ADC, SNR is measured in the frequency domain and calculated with a Fast Fourier Transform (FFT). The signal-to-noise ratio equals the ratio of the fundamental component of the signal (rms amplitude) to the rms level of the noise. Noise is the sum of all other spectral components, including harmonic distortion, but excluding dc. Although the signal being sampled does not have a significant slew rate at the instant it is encoded, dynamic performance of the ADC and the system is still critical. Transient response is
40 -55 C 35
6.4
5.5
30 0.1
1 10 INPUT FREQUENCY - MHz
100
Figure 7. Dynamic Performance vs. Analog Input Frequency
-8-
REV. D
EFFECTIVE NUMBER OF BITS (ENOB)
SIGNAL-TO-NOISE RATIO (SNR) - dB
AD9058
MECHANICAL INFORMATION
Die Dimensions . . . . . . . . . 106 mils x 108 mils x 15 ( 2) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 4 mils x 4 mils Metallization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VS Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride Die Attach . . . . . . . . . . . . . . . . . . . . Gold Eutectic (Ceramic) Bond Wire . . . . . . . . . 1 mil-1.3 mil, Gold; Gold Ball Bonding
-VS
ENCODE
-VREF
+VS
D7 (MSB)
D6
D5
D4
D3
D2
AIN +VS GROUND +VREF +VINT COMP +VREF GROUND +VS AIN
D1
D0 (LSB) GROUND -VS GROUND +VS +VS GROUND -VS GROUND D0 (LSB)
D5
+VS
D6
REV. D
-9-
ENCODE
D7 (MSB)
-VS
-VREF
D4
D3
D2
D1
AD9058
OUTLINE DIMENSIONS 44-Lead Ceramic Leaded Chip Carrier -- J-Formed Leads [JLCC] (J-44)
Dimensions shown in inches and (millimeters)
0.078 (1.98) 0.054 (1.37)
0.040 (1.02) REF x 45 3 PLACES
28
0.025 (0.64) MIN
40
0.662 (16.82) SQ 0.628 (15.95)
39 29
0.020 (0.51) REF x 45
0.032 (0.81) 0.020 (0.51)
0.650 (16.51) 0.610 (15.49)
0.023 (0.58) 0.013 (0.33)
0.050 (1.27) BSC
PIN 1 INDEX 0.065 (1.65)
PIN 1
TOP VIEW
0.500 (12.70) 0.492 (12.50)
BOTTOM VIEW
6 7 17
18
0.135 (3.43) 0.100 (2.54)
0.700 (17.78) SQ 0.680 (17.27)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
48-Lead Side-Brazed Solder Lid Ceramic DIP [DIP/SB] (D-48)
Dimensions shown in inches and (millimeters)
0.005 (0.13) MIN
48
0.098 (2.49) MAX
25
0.620 (15.75) 0.590 (14.99) PIN 1
1 24
0.225 (5.72) MAX
2.424 (63.57) MAX
0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN
0.630 (16.00) 0.520 (13.21)
0.200 (5.08) 0.125 (3.18)
0.023 (0.58) 0.014 (0.36)
0.110 (2.79) 0.090 (2.29)
0.070 (1.78) 0.030 (0.76)
SEATING PLANE
0.015 (0.38) 0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
-10-
REV. D
AD9058 Revision History
Location Page
5/03--Data Sheet changed from REV. C to REV. D Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6/01--Data Sheet changed from REV. B to REV. C Edits to ELECTRICAL CHARACTERISTICS headings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to Pinout captions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to Layout section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
REV. D
-11-
-12-
C00562-0-5/03(D)
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